View MAX100EVKIT_357718.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-0330; Rev 0; 11/94
MAX100 Evaluation Kit
_______________General Description
The MAX100 evaluation kit (EV kit) allows high-speed digitizing of analog signals at 250Msps, using the MAX100 ADC. All circuitry required to support the ADC is supplied. Data output is available in three formats: divide-by-1, divide-by-2, or divide-by-5 mode. Clocking is provided by an external clock source input through an SMA connector. The MAX100 EV kit main board comes complete with a MAX100 high-speed, 8-bit flash ADC with strobed comparators, latched outputs, and an internal track/hold. Analog input to the board is through two SMA coaxial connectors, for use with either differential or singleended inputs. Signals from the main board include dual-output data paths that allow easy interfacing to external circuitry. These two outputs can be configured either to provide two identical fast outputs (A and B), or an 8-to-16 demultiplexer mode that reduces the output data rates to one-half the sample clock rate. This demux is internal to the MAX100 ADC and is one of the key features of this device. A termination board with 50 ECL pull-down resistors is also supplied, and is connected to the main board with a 3x32 pin EURO-card connector. It provides access to the converter output data and provides proper ECL data termination. In addition to the pull-down resistors, this board has two ranks of square pins, each providing eight differential data outputs plus clock outputs. Either AData or BData may be observed with a high-speed logic analyzer. Standard power supplies of +5V and -5.2V are needed to operate the MAX100 EV kit board. Power can be supplied through the 3x32 EURO-card connector or through the pads on the edge of the board. Nominal power dissipation for both boards is 12W. The board set comes fully assembled and tested, with the MAX100 installed.
____________________________Features
o 6.8 Effective Bits at 125MHz o On-Board Reference Generator/Buffer o 50 Input Through SMA Coaxial Connectors o Dual Differential-Output Data Paths o 270mV Input Signal Range o Latched 100k ECL Outputs o 3x32 Pin EURO-Card Connector
Evaluates: MAX100
______________Ordering Information
PART MAX100EVKIT TEMP. RANGE 0C to +70C BOARD TYPE Multi-Layer
______________________________EV Kit
________________________________________________________________ Maxim Integrated Products
1
Call toll free 1-800-998-8800 for free literature.
MAX100 Evaluation Kit Evaluates: MAX100
____________________Component List
DESIGNATION QTY U5 U2, U3, U4 U9 U6 Install on back of board behind U6 U7 U8 D1, D2 D3 C25, C27 C2, C6, C9 C1, C3, C5, C8, C11, C12, C14, C16, C18, C20, C22-C24, C26, C28, C29 C13, C15, C17, C19, C21, C30 C4, C7, C10 SW1 L1, L2 R14, R15 R18, R19 R7, R8, R13, R20-R45 R1, R3, R6 R5, R10 R9 R2, R4 R16, R17 R11, R12 J1, J2, J3 J4 None 1 3 1 1 1 1 1 2 1 2 3 DESCRIPTION Motorola MC100E116 (quintuple line receiver) Motorola MC100E151 (Hex D flip-flop) Motorola MC100E157 (quadruple 2:1 multiplexer) LM337T negative voltage regulator Insulating washer Maxim MAX412CPA Maxim MX580KH Central Semiconductor CMPSH-3 Central Semiconductor CMPD4448 0.22F ceramic SMD capacitors 0.1F ceramic SMD capacitors
_________________________Quick Start
1) Plug the termination board into the 96-pin connector of the MAX100 EV kit board. 2) Use a fan to provide at least 200 lineal feet per minute airflow to the MAX100's heatsink. 3) Connect the power supplies. The power-supply input pads are in the lower right corner of the MAX100 EV kit board. The board requires a 12W power supply that provides +5V and -5.2V with a common ground. 4) Turn on the -5.2V power supply, followed by the +5V power supply. The -5.2V power supply should be the first supply turned on and the last supply turned off. 5) Connect a low-phase-jitter RF source with an input range of -4dBm to +10dBm to the clock input. 6) Connect a test signal to the analog inputs. Use IN+ and IN- if the signal is differential, or use IN+ if the signal is single-ended. 7) Use a logic analyzer (such as the HP8000 or an equivalent data-acquisition system) to observe the digitized results on the termination board pins. The outputs are 100k ECL compatible.
16
0.01F ceramic SMD capacitors
_______________Detailed Description
Board Set
The MAX100 EV kit is a two-board set. The first contains ECL-interface circuitry and the MAX100 ADC. The second (termination board) provides for high-speed signal termination and access to the data. For further signal processing, the board containing the MAX100 can be plugged into a larger customer system via the provided EURO-card connector.
6 3 1 2 2 2 29 3 2 1 2 2 2 3 1 1
100pF ceramic SMD capacitors 10F surface-mount tantalum capacitors 8-pin dip switch Surface-mount ferrite bead 20, 5% surface-mount resistors 27.4, 1% surface-mount resistors 51, 5% surface-mount resistors 82.5, 1% surface-mount resistors 121, 1% surface-mount resistors 150, 1% surface-mount resistor 221, 1% surface-mount resistors 12.1k, 1% surface-mount resistors 100 trim pots Female SMA connectors 96-pin EURO-style plug MAX100 clamp kit
Clock Input
The ADC clock is provided through an external clock input. The external clock supplied to the board must be very stable, with low phase jitter (-150dBc/Hz at 0.2kHz from fundamental) for best effective bits performance. Figure 2 in the MAX100 data sheet shows the input to output clock and data timing relationships. The MAX100 will accurately operate with low-repetitionrate clocks (DC to 250MHz) as long as the proper tpwl is observed (nominally 2ns to 5ns). Refer to Figures 1-4 in the MAX100 data sheet for further information.
Analog Input
Analog input to the ADC is made through one or both of the SMA coaxial connectors (IN+, IN-) provided. Each input is a direct connection to the ADC. 50 terminations are provided (at AIN+ and AIN- inputs) internal to the MAX100 ADC. Optimum performance is achieved
2
_______________________________________________________________________________________
MAX100 Evaluation Kit
by using the converter in differential input mode. Single-ended drive is handled by choosing either input, and leaving open or terminating the other in the system characteristic impedance. In this mode, the unused input can provide a DC offset to the incoming signal. (See the Electrical Characteristics in the MAX100 data sheet for this DC voltage range.) To obtain a digital output of all ones (11....1) with differential input drive, apply 270mV between AIN+ and AIN-. That is, AIN+ = +135mV and AIN- = -135mV (when no DC offset is applied). Mid-scale digital output code occurs when there is no voltage difference across the analog inputs. Zero-scale digital output code, with differential drive, occurs when AIN+ = -135mV and AIN- = +135mV. The converter's output stays at all ones (full scale) or all zeros (zero scale) when over-ranged or under-ranged, respectively. Table 1 shows these relationships. low 146 input impedance of this string will draw approximately 14mA. A reference voltage of nominally 1.02V is set by trim pots R11 and R12 at the factory, and can be measured at the VARTS and VARBS sense input pins. This reference controls the comparator input windows, and can be adjusted between 1.4V to accommodate other reference voltages (MAX100 accuracy specifications are based on a reference voltage of 1.02V).
Evaluates: MAX100
DIV, MOD, A=B
Three dip switches (SW1), DIV, MOD, and A=B, program converter operation and the characteristics of the two output data paths. Six options are available, but the normal operating configuration is set to 0 0 1 on the A=B, MOD, and DIV switches, respectively (Table 2). This gives the most current sample at AData, with the older data on BData. Both outputs are synchronous and are output at half the input clock rate. Figure 4 shows the location of these switches on the ADC board. Refer to Table 1 for mode-selection instructions.
Digital Outputs
The MAX100 EV kit provides complementary ECL digital outputs. Data output from the ADC is available in several selectable options (Table 2). Two 8-bit-wide data paths from the ADC are latched in D flip-flops (MC100E151), and are provided as unterminated differential outputs at the 3x32 pin EURO-card connector on the main board. Output timing clocks DCLK and DCLK are also available unterminated at the connector.
Power Supplies
Two supplies are needed for normal operation of both boards with a device installed: +5V at 0.6A and -5.2V at 1.7A. The pads APOS1 and ANEG1 are located in the lower right corner of the ADC board, and are labeled accordingly. The ADC runs off both supplies. Power may also be applied at the EURO-card connector pins, which are labeled as follows: VCC (+5V), VEE (-5.2V for digital DNEG1), VAA (-5.2V for analog ANEG1), and AGND (AGND1 ground). The ferrite beaded jumper (L1) in the lower right corner of the board connects VAA and VEE for a single -5.2V supply.
Clock Phasing
The MAX100 contains an internal track/hold (T/H) amplifier. The differential inputs, AIN+ and AIN-, are tracked continuously between data samples. When a negative CLK is applied, the T/H enters the hold mode. When CLK reaches the low state, the just-acquired sample is presented to the ADC's input comparators. After additional clock cycles required for internal processing, the sampled data is available at the AData or BData outputs. All output data is timed from the output clocks, DCLK and DCLK. (See Figure 2 in the MAX100 data sheet.)
Board Layout
The MAX100 requires proper PC board layout for device operation. This section explains the layout requirements and demonstrates how the EV kit achieves these goals. Use power and ground planes to deliver power to the devices, keeping the digital planes separate from the analog planes. The EV kit uses layers 3, 4, and 5 for power and ground planes. Tie digital ground and analog ground together at a single point, as close to the power supply as possible. On the EV kit, digital ground ties to analog ground at ferrite bead L1. Likewise, tie digital power (VEE) and analog power (VAA) together at a single point, as close to the power supply as possible. On the EV kit, digital power ties to analog -5.2V power at ferrite bead L2. Use transmission lines for the analog input and for the high-speed digital outputs. The MAX100 EV kit uses 50 microstrip lines that occupy layers 1 and 2, and
ADC Reference Resistors
An on-board reference supply and op-amp circuit drive the ADC reference-resistor string. Adjustments can be made through the two potentiometers provided. After the MAX100 ADC is installed, follow the Calibration Procedure. Buffer amplifiers are used to drive the top and bottom inputs of the reference-resistor string. (The resistor string center-tap is not made available for adjustment on this board.) A 2.5V reference (MX580KH) is divided down and buffered through a MAX412 op amp. The relatively
_______________________________________________________________________________________
3
MAX100 Evaluation Kit
FR4 epoxy dielectric material with a relative dielectric constant between 4.1 and 4.9. The nominal design has a foil thickness of 0.0014 inch (0.0355 mm) for layer 1 (the signal layer) and 0.0014 inch (0.0355 mm) for layer 2 (the ground return). Dieletric thickness between layers is nominally 0.011 inch (0.28 mm), with a signal trace width of 0.020 inch (0.50 mm). Refer to Motorola's MECLTM or ECLinPSTM data book for an introduction to microstrip design. Due to the high-speed nature of this part, the propagation delay of the PC board traces becomes a significant design consideration. For the EV kit design, the propagation delay is approximately 145ps per inch (5.7ps/mm). For best results, try to match the lengths of the data traces to within 0.5 inch (12 mm). The EV kit board matches the data-bus lengths by using curved traces on layer 6. A computer-aided design system can be helpful in measuring the trace lengths accurately. The clock signal must be routed on one layer only, without using any throughhole vias. The MAX100 EV kit is a controlled-impedance board (50) and has a total board thickness of 0.062 inches (1.57 mm) using six copper layers (Figure 3).
Evaluates: MAX100
Table 1. Input Voltage Range
INPUT AIN+** (mV) AIN-** (mV) -135 0 +135 0 0 0 OUTPUT CODE 11111111 10000000 00000000 11111111 10000000 00000000 (MSB TO LSB) Full scale Mid scale Zero scale Full scale Mid scale Zero scale
+135 Differential 0 -135 SingleEnded +270 0 -270
** An offset, VIO, as specified in the DC Electrical Characteristics, is present at the input. Compensate for this offset either by adjusting the reference voltage VART, VARB, or by introducing an offset voltage in one of the input terminals, AIN+ or AIN-.
Table 2. Output-Mode Control
DIV MOD A = B DCLK* Divide-by-1 Mode 0 X 0 Data appears on AData only. 250MHz BData port inactive (see Figure 3 of MAX100 data sheet). 250MHz AData identical to BData (see Figure 3 of MAX100 data sheet). DESCRIPTION
Testing
We recommend that a digital acquisition instrument like the HP8000 logic analyzer be used to acquire and process the output data. At Maxim, the data acquired from the converter is evaluated in an effective-bits software program developed in-house. The effective-bits measurement is a good tool to determine and compare ADC accuracy.
0
X
1
Divide-by-2 Mode 8:16 demux mode. AData and BData ports are active. BData 125MHz carries older sample and AData carries most recent sample (see Figure 4 of MAX100 data sheet). AData and BData ports are active. Both carry identical sam125MHz pled data. Alternate samples are taken but discarded. AData port updates data on 5th input CLK. BData port inactive. The other four sampled data points are discarded. AData and BData ports are both active with identical data. Data is updated on output ports every fifth input clock (CLK). The other four samples are discarded.
_____________Calibration Procedure
The MAX100 EV kit comes ready to operate from the factory. If other devices are to be used in the same fixture, the EV kit should be recalibrated according to the following procedure: 1) With the ADC removed, adjust the +5V and -5.2V supplies. 2) Set the mode-select options (A=B, DIV, MOD) for the desired operation using the on-board DIP switches. See Table 1. 3) With the power off, insert the MAX100. The MAX100's heatsink fits down through the board with the device leads resting on top. Be sure to place the part in the board with pin 1 in the correct location. Provide at least 200 lineal feet per minute airflow whenever power is applied. Turn on the power supplies with -5.2V first, then the +5V. The -5.2V power supply should be the first supply turned on and the last supply turned off.
TM MECL and ECLinPS are trademarks of Motorola Corp. 4
1
0
0
1
0
1
Divide-by-5 Mode 1 1 0 50MHz
1
1
1
50MHz
* Input clocks (CLK, CLK) = 250MHz for all above combinations. In divide-by-2 or divide-by-5 mode, the output clock DCLK is always a 50% duty-cycle signal. In divide-by-1 mode, DCLK has the same duty cycle as CLK.
_______________________________________________________________________________________
MAX100 Evaluation Kit
4) After the part has warmed up for several minutes, adjust the reference voltages to 1.02V nominally. The test points for these voltages are at the bottom of the sense resistors, R13 and R16, located just above the sense pins VARTS and VARBS (Figure 4). 5) Adjust mid-code level. With no analog input (AIN+ (AIN-) = 0V) the output code should match that specified in Table 1. If there is an offset, adjust either the positive or negative reference until the expected code
U8 1 MX580KH TO-52 +VS
VOUT GND 3 AGND R11 100 2
of 10 00 00 00 (MSB to LSB) is achieved. After adjusting to the proper level, the references need to be balanced to 1.02V around any offset that was introduced. (If the negative reference was moved by +32mV, the positive reference must be moved by that same amount to ensure the correct LSB size.) It may be necessary to repeat the reference offset adjustment again after the correct 2.04V differential reference voltage is re-established around the common-mode offset.
Evaluates: MAX100
REFERENCE VOLTAGE GENERATOR VCC C23 0.01F AGND VARTS 2 1 C24 ADJREF+1 0.01F R9 150, 1% R12 100 R10 121, 1% ADJREF+1 AGND ADJREF-1 R17 12.1k 1% 6 7 5 3 C26 0.01F R14 20, 5% C25 0.22F AGND AGND R16 12.1k 1% VARBS C28 0.01F R15 20, 5% C27 0.22F AGND AGND R19 27.4, 1% D2 SOT-23 CMPSH-3 VARB R13 51, 5% R18 27.4, 1% D1 SOT-23 CMPSH-3 VART
2.5VREF
U7A MAX412CPA DIP8
TO MAX100
U7B MAX412CPA DIP8
POWER-SUPPLY BYPASSING ANALOG +5.0V APOS1 C3 0.01F C5 0.01F C2 0.1F C6 0.1F C4 10F, 10V C7 10F, 10V FERRITE L2 VAA FERRITE L1 DIGITAL +5.2V DNEG1 C8 0.01F C9 0.1F C10 CAP 10F, 10V VEE VCC MODE SELECT SWITCHES D3 CMPD4448 SW1 1 2 3 GND 4 DIP8 BYPASS CAPACITORS NEAR U1 C12 VCC 0.01F PIN 8 C13 AGND 100pF VEE PIN 32 0.01F C21 100pF GND C20 VTT GENERATOR C18 VCC PIN 43 0.01F C19 100pF VAA PIN 80 0.01F C17 100pF AGND VEE -5.2V AGND VAA PIN 69 0.01F C15 C16 100pF AGND C14 1 C11 0.01F R6 82.5 1% GND VTT 8 7 6 5 A=B MOD DIV
ANALOG GROUND
AGND1
AGND
GND
ANALOG -5.2V
ANEG1
U6 LM337T TO-220
ADJ
OUT IN 2
3
R5 121 1% -2.0V TO TERMINATING RESISTORS
Figure 1. MAX100 EV Kit Schematic
_______________________________________________________________________________________ 5
MAX100 Evaluation Kit Evaluates: MAX100
ANALOG PLANES NOTES: 1. WHERE INDICATED, MATCH BUS LENGTH TO WITHIN 0.5". 2. UNLESS OTHERWISE SPECIFIED, ALL RESISTORS AND CAPACITORS ARE 1206 SIZE. 3. NOTE SPECIAL MECHANICAL REQUIREMENTS OF MAX100, INCLUDING CUT-OUT FOR THE HEATSINK. DIGITAL PLANES C22 VTT 0.01F VTT R7-R8 51 VART GND VARB AGND B0 A0 B1 TO/FROM REFERENCE BUFFER
VARTS VARBS ANALOG PLANES DIGITAL PLANES
VCC GND
N.C. CLK CLK GND N.C. N.C. GND VCC VARB VARBS VACT VACTS VARTS VART GND N.C. B0 DGND A0 B1 VCC
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
J2 AGND J3 AGND INPUTINPUT+
VAA
VAA
PAD CLK CLK GND N.C. N.C. GND VCC N.C. N.C. DIV MOD DCLK DCLK GND A=B A7 DGND B7 A6 VCC
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 AGND
GND TP3 TP2 GND TP1 VEE GND GND AIN+ AIN+ GND AINAINGND GND GND VEE N.C. GND N.C. GND
U1 MAX100
NOTE MECHANICAL REQUIREMENTS
A1 B2 DGND A2 B3 DGND A3 N.C. DGND N.C. VEE N.C. DGND SUB B4 DGND A4 B5 DGND A5 B6
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
A1 B2 A2 B3 A3
VEE
B4 A4 B5 A5 B6 GND
VAA
DCLK DCLK
A7
C1 0.01F J1 SMA EXT CLK
R3 82.5 1%
R1 82.5 GND 1% 25 17 AGND VCC 26 18
VTT R42 51 GND VCC
R4 221 1% VEE
R2 221 1%
U5D MC100E116
VTT R43 51 ANALOG PLANES DIGITAL PLANES
VTT R44 51 25 23 22 21 20 19
DIV MOD
A=B
B7 A6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SEL3 NC D3A D3B VCC Q3 Q3
DIV 5 ROUTING INSTRUCTIONS: CLOCK LINE MUST ROUTE ON THE TOP LAYER, WITH NO VIAS. ATTEMPT TO MINIMIZE THE DISTANCE BETWEEN U4 CLOCK AND U2 CLOCK PINS. MATCH LENGTHS OF MAX100 TO '151 DATA BUS TO WITHIN 0.500". TERMINATIONS FOR MAX100-TO-151 DATA BUS SHOULD BE PAST THE 151 PINS. DISTANCE FROM 151 PIN TO TERMINATION IS NOT CRITICAL. MATCH LENGTHS OF ;151-TO-EURO CONNECTOR BUS TO WITHIN 0.500". VTT R41-R40 50 6 11 12
PCK NCK
U5B MC100E116
Figure 1. MAX100 EV Kit Schematic (continued)
6 _______________________________________________________________________________________
5 SEL0 6 D0A 7 D0B NC NC NC 11 VCC
26 27 28 1 2 DCLK 3 DCLK 4
D2B D2A SEL2 VEE SEL1 D1A D1B
U9 MC100E157
Q2 Q2 VCC Q1 Q1 Q0 Q0
18 17 16 15 14 13 12
VTT R45 50 FFCLK
MAX100 Evaluation Kit Evaluates: MAX100
96-PIN EURO CONNECTOR DATA VTT 21 20 NB0 19 PB0 PB0 J4-A1 J4-A2 J4-B1 J4-B2 NB0 DATA LABEL J4-C1 J4-C2 VTT B0
VTT R23 51 FFCLK VTT R20 51 25 24 23
MR CPB CPA N.C. VCC0 Q5 Q5
N.C. VCCO Q0 Q0 Q1 Q1 VCC0
B0 26 D5 A0 27 D4 B1 28 1 D3 VEE A1 2 D2 B2 3 D1 A2 4 D0
U2 MC100E151
Q4 Q4 VCC Q3 Q3 Q2 Q2
18 17 16 15 14 13 12
NA0 PA0 NB1 PB1 NA1 PA1
NA0 PA0 J4-A3 J4-B3 NB1 PB1 PA1 J4-A4 J4-A5 J4-B4 J4-B5 NB2 PB2 PA2 J4-A6 J4-A7 J4-A8 GND J4-B6 J4-B7 NB3 NA2 NA1
J4-C3
A0
J4-C4 J4-C5
B1 A1
PA2 NA2 PB2 NB2
6 7 8 9 10 11
J4-C6 J4-C7 J4-C8
B2 A2 B3
VTT R24-R29 51 R21 51 21 20 NB3 19 PB3 VTT 25 24 23
PB3
J4-B8
MR CPB CPA N.C. VCC0 Q5 Q5
N.C. VCCO Q0 Q0 Q1 Q1 VCC0
B3 26 D5 A3 27 D4 B4 28 1 D3 VEE A4 2 D2 B5 3 D1 A5 4 D0
U3 MC100E151
Q4 Q4 VCC Q3 Q3 Q2 Q2
18 17 16 15 14 13 12
NA3 PA3 NB4 PB4 NA4 PA4
NA3 PA3 J4-A9 J4-A10 PB4 PA4 J4-A11 J4-A12 J4-B9 J4-B10 J4-B11 J4-B12 NB5 PB5 PA5 J4-A13 J4-A14 J4-B13 J4-B14 NA5 NB4 NA4
J4-C9 J4-C10 J4-C11 J4-C12
A3 DGND B4 A4
PA5 NA5 PB5 NB5
6 7 8 9 10 11
J4-C13 J4-C14
B5 A5
25 24 23
MR CPB CPA N.C. VCC0 Q5 Q5
21 20 19
VTT R30-R35 51
R22 51 VTT
N.C. VCCO Q0 Q0 Q1 Q1 VCC0
26 D5 B6 27 D4 A6 28 1 D3 VEE B7 2 D2 A7 3 D1 4 D0
U4 MC100E151
Q4 Q4 VCC Q3 Q3 Q2 Q2
18 17 16 15 14 13 12
NB6 PB6 NA6 PA6 NB7 PB7
NB6 PB6 J4-A15 J4-B15 NA6 PA6 PB7 J4-A16 J4-A17 J4-B16 J4-B17 NA7 PA7 NB7
J4-C15
B6
J4-C16 J4-C17
A6 B7
6 7 8 PA7 9 NA7 10 11
J4-C18 J4-C19 J4-C20 J4-C21 J4-C22 J4-C23 J4-C24 J4-C25 J4-C26 J4-C27 J4-C28 J4-C29 J4-C30 J4-C31 J4-C32
A7 CLOCK MODE RESERVED VEE
FFCLK
VTT R36-R39 51
PCK A=B
SIGNAL DISTRIBUTION LAYER 1 2 3 4 5 6 DIGITAL AREA SIGNALS GND VTT (-2V) VEE (-5.2V) GND SIGNALS ANALOG AREA SIGNALS AGND VCC (+5V) VAA (-5.2V) AGND SIGNALS
VEE
VAA VCC
AGND
J4-A18 J4-A19 J4-A20 DIV J4-A21 J4-A22 J4-A23 J4-A24 J4-A25 J4-A26 J4-A27 J4-A28 J4-A29 J4-A30 J4-A31 J4-A32 AGND
J4-B18 J4-B19 J4-B20 J4-B21 J4-B22 J4-B23 J4-B24 J4-B25 J4-B26 J4-B27 J4-B28 J4-B29 J4-B30 J4-B31 J4-B32
NCK MOD
VAA VCC
AGND
AGND
Figure 1. MAX100 EV Kit Schematic (continued)
_______________________________________________________________________________________ 7
MAX100 Evaluation Kit Evaluates: MAX100
DIV = 0
1.0ns DCLK from MAX100 2.0ns 3.0ns 4.0ns
2.4ns DATA at MAX100 0.8ns OLD DATA VALID DATA
DATA at D FLIP-FLOP INPUTS FIRST D FLIP-FLOP CLOCK
(0.145ns/inch) (1.363" to 1.844") VALID DATA
(2.676") + (220ps to 550ps)
DATA HOLD TIME
DIV = 1
DCLK from MAX100 1.4ns DATA at MAX100 VALID DATA 0.1ns VALID DATA
DATA at D FLIP-FLOP INPUTS
VALID DATA
FIRST D FLIP-FLOP CLOCK DATA HOLD TIME
Figure 2. Evaluation Kit Timing
8 _______________________________________________________________________________________
MAX100 Evaluation Kit Evaluates: MAX100
Copper Layer 1 Copper thickness = 0.0014" (1 oz copper) Epoxy FR4 Dielectric layer thickness = 0.01072"
Copper Layer 2 Copper thickness = 0.0014" (1 oz copper) Epoxy FR4 Dielectric layer thickness = 0.01072"
Copper Layer 3 Copper thickness = 0.0014" (1 oz copper) Epoxy FR4 Dielectric layer thickness = 0.01072"
Copper Layer 4 Copper thickness = 0.0014" (1 oz copper) Epoxy FR4 Dielectric layer thickness = 0.01072"
Copper Layer 5 Copper thickness = 0.0014" (1 oz copper) Epoxy FR4 Dielectric layer thickness = 0.01072"
Copper Layer 6 Copper thickness = 0.0014" (1 oz copper)
Microstrip traces are 20 mils wide for 50 impedance.
Figure 3. Layer Profile
Figure 4. Main Board Component Placement Guide-- Component Side
Figure 5. Main Board Component Placement Guide-- Solder Side
Figure 6. Main Board Layout--Copper Layer 1 (Top)
_______________________________________________________________________________________
9
MAX100 Evaluation Kit Evaluates: MAX100
Figure 7. Main Board Layout--Copper Layer 2 (negative image)
Figure 8. Main Board Layout--Copper Layer 3 (negative image)
Figure 9. Main Board Layout--Copper Layer 4 (negative image)
Figure 10. Main Board Layout--Copper Layer 5 (negative image)
10
______________________________________________________________________________________
MAX100 Evaluation Kit Evaluates: MAX100
6.000" (152mm)
5.000" (127mm)
NOTE: THE MAX100 CUT-OUT IS 1.18" SQUARE
SIZE QTY SYM + 20 132 37 138 X 125 11 70 12 Y 60 3 Z
Figure 11. Main Board Layout--Copper Layer 6 (Bottom)
Figure 12. Main Board Mechanical Outline
TERM BOARD MAX100EVKIT MAX101EVKIT SIGNAL SIGNAL SIGNAL T1 F1 T2 F2 T3 F3 T4 F4 T5 F5 T6 F6 T7 F7 T8 F8 T9 F9 T10 F10 T11 F11 T12 F12 T13 F13 T14 F14 T15 F15 T16 F16 T17 F17 B0 B0 A0 A0 B1 B1 A1 A1 B2 B2 A2 A2 B3 B3 A3 A3 B4 B4 A4 A4 B5 B5 A5 A5 B6 B6 A6 A6 B7 B7 A7 A7 DCLK DCLK A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 DCLK DCLK A7 A7 B7 B7 B6 B6 B5 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0
Figure 13. Termination Board Component Placement Guide and Signal Connections--Component Side
Figure 14. Termination Board Component Placement Guide--Solder Side
11
______________________________________________________________________________________
MAX100 Evaluation Kit Evaluates: MAX100
2, 3
Figure 15. Termination Board Layout--Layer 1
Figure 16. Termination Board Layout--Layers 2, 3
2.000" (25.8mm)
50 MICROSTRIP LAYER PROFILE 0.020" 1OZ COPPER 0.0014" FR4 E = 4.1-4.9 1OZ COPPER 4.500" FR4 E = 4.1-4.9 (114.3mm) 1OZ COPPER 0.010" 0.0014"
0.010" 0.0014" FR4 E = 4.1-4.9 0.010" 0.0014" 1OZ COPPER 0.020"
Figure 17. Termination Board Layout--Layer 4 (Bottom)
Figure 18. Termination Board Mechanical Guide
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1994 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX100EVKIT

	To Download MAX100EVKIT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .